# 22V10 for Rack8 SelfScan interface

Device 22V10

input
    Clock_in:1,	             # The clock, which we develop on pin-23, for our registered outputs
    SC1:2,                   # These are the inputs from the Sync Counter
    SC2:3,		     # "
    SC4:4,		     # "
    SC8:5,		     # "
    SC16:6,		     # "
    SC32:7,		     # "
    Phase2:8,                # Phase2 from the CPU clock
    S0:9,                    # Status lines from the CPU
    S1:10,                   # "
    S2:11,                   # "
    Sync:13,                 # From the CPU
    Rco_FF_Active:14,        # The Q output from the Rco_Watcher FF which is set when
                             #   RCO from the SSAC goes true. This is the cue which prompts us,
                             #   at the start of the next SS clock period, to initiate a reset
                             #   of the SS.
    SS_Reset_FF_Active:22,   # From the SS Reset FF	

output
    SC_RESET:16,             # Rising edge resets Sync Counter to zero
    Read_SS.L:17,	     # Signal to memory saying we are reading SelfScan data
    SSAC_Count:21,           # Rising edge tells SSAC to count
    Clock_out:23,            # The clock we develop for use by our registered outputs    

register
    SS_Reset_FF_Set.L:15,    # Used to set the FF that creates the SS reset pulse
    Data_Enable.L:18,        # Signal to enable data to the SelfScan
    SS_Reset_FF_Clr.L:19,    # Used to clear the FF that creates the SS reset pulse
    SS_Clock.L:20, 	     # Clock line to the selfscan

temp
    Count_00, Count_01, Count_02, Count_03, Count_04, Count_05, Count_06, Count_07, Count_08, Count_09,
    Count_56, Count_55,
    t_T1, t_STOP, t_WAIT,        

implementation

Count_00  equ !SC1 & !SC2 & !SC4 & !SC8 & !SC16 & !SC32
Count_01  equ  SC1 & !SC2 & !SC4 & !SC8 & !SC16 & !SC32
Count_02  equ !SC1 &  SC2 & !SC4 & !SC8 & !SC16 & !SC32
Count_03  equ  SC1 &  SC2 & !SC4 & !SC8 & !SC16 & !SC32
Count_04  equ !SC1 & !SC2 &  SC4 & !SC8 & !SC16 & !SC32
Count_05  equ  SC1 & !SC2 &  SC4 & !SC8 & !SC16 & !SC32
Count_06  equ !SC1 &  SC2 &  SC4 & !SC8 & !SC16 & !SC32
Count_07  equ  SC1 &  SC2 &  SC4 & !SC8 & !SC16 & !SC32
Count_08  equ !SC1 & !SC2 & !SC4 &  SC8 & !SC16 & !SC32
Count_09  equ  SC1 & !SC2 & !SC4 &  SC8 & !SC16 & !SC32

Count_55  equ  SC1 &  SC2 &  SC4 & !SC8 &  SC16 &  SC32
Count_56  equ !SC1 & !SC2 & !SC4 &  SC8 &  SC16 &  SC32

t_T1   equ !S0 &  S1 & !S2
t_STOP equ  S0 &  S1 & !S2
t_WAIT equ !S0 & !S1 & !S2 

# When the sync counter reaches 56 (56 x 2.5 uS per sync pulse = 140 us which
#   is the desired SS clock period) we reset it to start counting at zero

SC_RESET equ Count_56

# This is the clock pulse that tells the SelfScan Address Counter
#   to advance by one.

SSAC_Count equ Count_00 & SYNC & Phase2

# The clock we use for our registered outputs

Clock_Out equ Sync & Phase2

# Clock data from memory into the SS Data Latch when the CPU is in state T1, Stop or Wait.

Read_SS     equ (t_T1 | t_STOP | t_Wait) & Sync & Phase2

# Enable the SS_Data_Latch to the SS aux data inputs unless a SS reset is in progress
#   or we are within the first 15 uS (6 x 2.5 us = 15) of a SS clock period.

Data_Enable equ ! (SS_Reset_FF_Active | Count_00 | Count_01 | Count_02 | Count_03 | Count_04 | Count_05)

# Set the SS reset FF at Count=1 if the input from the RCO catcher is true.
#   This initiates a one-SS-clock-perior reset to the SS.

SS_Reset_FF_Set equ Rco_FF_Active & Count_01

# We clear the SS_Reset FF at count-55 for every SS clock period. We really only
#  need to clear it when a SS reset is in progress, but clearing it when it is
#  already clear does no harm and we have no way, inside this 16V22, of knowing when
#  a SS reset is in progress, and we have no available inputs to find out.

SS_Reset_FF_Clr equ Count_55

# The clock to the SS. For the first 10 counts (10 x 2.5 uS = 25uS) we assert the
#   clock, for the rest of the period we deassert the clock.

SS_Clock    equ Count_00 | Count_01 | Count_02 | Count_03 | Count_04 | Count_05 | Count_06 | Count_07 | Count_08 | Count_09