# 16V8 for I/O number zero

Device 16V8 #In combinitorial mode

input
    GATE:1,         # Signal from our GATE FF
    PH2:2,          # CPU clock phase 2
    PINT:3,         # Processing interrupt from CPU
    T3IO:4,         # Flags T3 state for IO read
    IOW.L:5,        # IO write from CPU
    A12:6,          # Address lines from CPU
    A11:7,
    A10:8,
    A9:9,
                    # Pin 11 not used

temp
    adr_0, adr_1, adr_2, adr_3, adr_4, adr_5
   
        
output    
    GATE_CLR.L:12,  # Pulse to clear the GATE FF
    RESET.L:13,     # Master reset to anybody that needs it
    DBG1.L:14,      # Write-read debug latch one
    DBG0.L:15,      # Write-read debug latche zero
    GDI.L:16,       # Gate data in (read omniport data)
    GSI.L:17,       # Gate status in (read omniport status)
    SYS.L:18,       # Write-read system latch
    KBD.L:19        # Write-read keyboard
    
implementation

adr_0 equ !A11 & !A10 & !A9
adr_1 equ !A11 & !A10 &  A9
adr_2 equ !A11 &  A10 & !A9
adr_3 equ !A11 &  A10 &  A9
adr_4 equ  A11 & !A10 & !A9
adr_5 equ  A11 & !A10 &  A9

# We want to clear the GATE FF when after the IO read is over
GATE_CLR equ !T3IO & PH2

KBD  equ Adr_0 & GATE
SYS  equ Adr_1 & GATE
GSI  equ Adr_2 & GATE
GDI  equ Adr_3 & GATE
DBG0 equ Adr_4 & GATE
DBG1 equ Adr_5 & GATE

# If we are processing an interrupt then it's RESET time
RESET     equ !PINT