#===========================
Device 16V8 # For Omnisnort3
#===========================

input
    MegaNext.H:1,       #Next pulse from Mega
                        #Input 2 not used
    MegaMode0.H:3,      #Mode-0 from Mega
    Seqbit0.H:4,        #Q-0 from sequence counter
    SeqBit1.H:5,        #Q-1
    SeqBit2.H:6,        #Q-2
    SeqBit3.H:7,        #Q-3
    SeqBit4.H:8,        #Q-4
    MegaMode1.H:9,      #Mode-1 from Mega
    Wsfull.H:11         #Wsfull from RAM address counter

# Mode0 Mode1 What
# ----- ----- -----
#   0     0   Read       - Return captured data to Arduino
#   0     1   Snort      - Capture data from Omniport 
#   1     0   Pre-write  - Get ready to let Arduino write to current memory address
#   1     1   Write      - Write Arduino data to current memory address

output
    Reset.L:12,          #Reset the sequence counter and the activity FF
    Snorting.H:13,       #Enable activity FF to allow snorting
    DataSourceSel2.H:14, #Data source select 2
    DataSourceSel1.H:15, #                   1
    DataSourceSel0.H:16, #                   0
    AddressClock.L:17,   #Clock to RAM address counter
    WriteRam.L:18,       #True to write to RAM
    TimeRegClock.H:19    #Timer register clock

temp
    #Create temporaries State00 through State18
    State/0..18,

    #The modes decoded
    ModeSnort, ModeRead, ModePreWrite, ModeWrite,
    
implementation

/*
 What happens when:

State Action
----- ------
   00 Idle
   01 Enable Omniport-control to RAM data bus
      Clock time-stamp data to the hold register
   02 Write RAM
   03 Advance RAM address counter
   04 Enable Omniport-data to RAM data bus
   05 Write RAM
   06 Advance RAM address counter
   07 Enable TS-3 to RAM data bus
   08 Write RAM
   09 Advance RAM address counter
   10 Enable TS-2 to RAM data bus
   11 Write RAM
   12 Advance RAM address counter
   13 Enable TS-1 to RAM data bus
   14 Write RAM
   15 Advance RAM address counter
   16 Enable TS-0 to RAM data bus
   17 Write RAM
   18 Reset Sequence counter and activity FF
      Advance RAM address counter

Data source select bits:

    Bit
  2  1  0   Source  States  Notes
  -------   ------  ------  -----
  0  0  0   None    -       Nothing enabled onto bus
  0  0  1   O-Ctrl  1 2     Omniport controls signals
  0  1  0   TS-0    15 16   Timestamp low byte
  0  1  1   TS-1    13 14   Timestamp next to low byte
  1  0  0   TS-2    10 11   Timestamp next to high byte
  1  0  1   TS-3    7 8     Timestamp high byte
  1  1  0   RAM     -       RAM enabled only in ModeRead
  1  1  1   O-Data  4 5     Omniport data signals
*/

#This implements State00 through State18 as the binary sequence of the given inputs
State seq 0..18  of SeqBit4 SeqBit3 SeqBit2 SeqBit1 SeqBit0

ModeSnort    equ !MegaMode0 &  MegaMode1
ModeRead     equ !MegaMode0 & !MegaMode1
ModePreWrite equ  MegaMode0 & !MegaMode1
ModeWrite    equ  MegaMode0 &  MegaMode1

Reset           equ State18
Snorting        equ ModeSnort & !Wsfull
AddressClock    equ State03 | State06 | State09 | State12 | State15 | State18 | (!ModeSnort & MegaNext 
                    & !Wsfull)
WriteRam        equ ((State02 | State05 | State08 | State11 | State14 | State17) & ModeSnort 
                    & !Wsfull) | ModeWrite    
TimeRegClock    equ State01
DataSourceSel0  equ (State01 | State02 | State04 | State05 | State07 | State08 | State13 
                    | State14) & ModeSnort
DataSourceSel1  equ ((State04 | State05 | State13 | State14 | State15 | State16) & ModeSnort) 
                    | ModeRead
DataSourceSel2  equ ((State04 | State05 | State07 | State08 | State10 | State11) & ModeSnort) 
                    | ModeRead